Thermal processing systems are widely used in various stages of semiconductor fabrication. Basic thermal processing applications include chemical deposition, diffusion, oxidation, annealing, silicidation, nitridation, and solder re-flow processes. Vertical rapid thermal processing (RTP) systems comprise a vertically oriented processing chamber which is heated by a heat source such as a resistive heating element or a bank of high intensity light sources. The heat source is capable of heating the interior of the processing chamber to temperatures in the range of 450-1400 degrees Centigrade (.degree.C.) at ramp rates of up to about 100.degree. C./sec.
One example of a vertical RTP system for treating a single wafer is shown in U.S. Pat. No. 4,857,689 to Lee, assigned to the assignee of the present invention and incorporated by reference as if fully set forth herein. The Lee patent discloses a process chamber which is heated by a resistive heating element located atop the chamber. The resistive heating element heats the process chamber so that a temperature gradient is obtained from the top of the chamber (hottest) to the bottom of the chamber (least hot). The chamber sidewalls exhibit this temperature gradient which, for the sidewalls, is obtained by (i) heat which is conducted down the sidewalls from the top of the chamber and (ii) heat which is radiated convectively through the chamber from the resistive heater. An elevator which supports a wafer is moved up and down within this temperature gradient by a process control system so that desired heating of the wafer occurs.
The single-heater construction such as that shown in Lee imposes process characteristics which may adversely affect the processing of a single wafer, as well as multi-wafer system throughput. Because the wafer and the pedestal upon which it is supported occupies a significant portion of the total vertical cross sectional area of the process chamber, the wafer and pedestal block heat radiating from the top resistive heating element, which prevents the blocked heat from reaching and heating the portion of the chamber below the wafer. Accordingly, during the processing of a single wafer, the sidewall temperature gradient may be characterized by significant temperature discontinuities, depending upon the particular sidewall location and the position of the wafer with respect to that location. Such temperature discontinuities render precise heating of the wafer difficult.
In addition, a single heater construction is also characterized by a sidewall temperature gradient which initially drifts and then stabilizes only after several wafers have been processed. This drift phenomenon slows start-ups and therefore reduces system throughput. It is suspected that, because the chamber sidewalls are heated by both convective and conductive heating, the extent of conductive heating progresses to such an extent after the processing of several wafers so as to reduce the adverse affect of radiant (convective) heat blockage by the wafer. After the successive processing of multiple wafers, this problem disappears. In some cases this problem has been accommodated by the initial processing of dummy wafers, which adversely affects system throughput. However, even the use of dummy wafers will not cure the sidewall temperature gradient discontinuity experienced during the processing of single wafers. That is, during processing of each individual wafer, the wafer still functions to block radiant heat and thus the sidewall temperature at a particular location fluctuates depending upon whether the wafer is located above or below that location.
Accordingly, it is an object of the present invention to provide a single wafer RTP vertical furnace using a plurality of continuous heat sources located at various vertical locations of the furnace to provide for a consistent and continuous temperature gradient within the chamber.
It is a further object of the present invention to provide such a furnace having an active sidewall heating mechanism for providing a consistent temperature reading at a particular vertical location of the sidewall, independent of the position of the wafer within the furnace, and independent of the number of wafers which have been processed.